The k-clustering problem under the criterion with a=1,2 are treated in a unified manner by characterizing the optimum solution to the kclustering problem by the ordinary Euclidean Voronoi diagram and the weighted Voronoi diagram with both multiplicative and additive weights. The cases of a=1,2 correspond to the sum of squared errors and the all-pairs sum of squared errors, respectively. As the inter-cluster criterion to minimize, the sum on intra-cluster errors over every cluster is used, and as the intra-cluster criterion of a clusterSj, a -1pi∈Sjxi-x Sj 2 is considered, where &dot is the L2 norm and xSj is the centroid of points in Sj, i.e., 1/Sjpi∈Sjxi. In this paper we consider thek-clustering problem for a set S of n points i=xi in thed-dimensional space with variance-based errors as clustering criteria, motivated from the color quantization problem of computing a color lookup table for frame buffer display. Generally, our work has better performance, improved efficiency and is more practical to be applied in the industry. The slew rate constraint is satisfied with a small clock skew from SPICE estimation. The experimental results show that the power cost of our work is smaller and the runtime is reduced. This ensures the limitation of the clock slew can be strictly satisfied while the limitation of the clock slew is always applied in the real design. In our work, the clock tree is constructed simultaneously with the insertions of clock gates. The clock slew changes a lot after the insertions of clock gates in real cases. Compared to previous works, clock tree synthesis is done first and followed by the insertions of clock gates. In PSACTS, a more practical clock slew constraint is applied. In PACTS, the topology of the clock tree is constructed with simultaneous buffer/gate insertion, which reduces the switched capacitance. In this paper, two novel gated clock tree synthesizers, power-aware clock tree synthesizer (PACTS) and power- and slew-aware clock tree synthesizer (PSACTS), are proposed with zero skew achieved based on Elmore RC model. Gated clock tree is an effective approach to reduce the dynamic power usage. © 2019 Institution of Engineering and Technology.All rights reserved.Ĭlock tree synthesis plays an important role on the total performance of chip. The experimental results so obtained are quite encouraging. Consequently, the proposed method is compared with recent existing works. The skew and dynamic power of the tree is calculated. Subsequently, an obstacle avoiding abstract clock tree is constructed with a minimum number of TSVs and buffers. The proposed method starts with a segregation technique to divide the sinks into smaller zones. The authors propose an algorithm for clock tree design based on the Elmore Delay method and routes all the sinks efficiently considering the obstacles with the use of an optimum number of through-silicon-vias (TSVs). The authors propose an algorithm to determine the performance of the clock network by optimising both the clock skew and the dynamic power consumption of the 3D IC clock tree. In this study, the authors present a 3D clock tree design algorithm to enhance the speed and performance of a VLSI chip. Compared with previous 3D clock tree synthesis techniques, our Kmeans clustering-based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.Įffective clock tree design is an important factor for determining chip performance. Experimental results indicate that (1) the K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity, and (2) the SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV's placement. In 3D-ICs, a shutdown gate is connected to a control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV's large physical dimension.We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering and (2) clock tree embedding with simultaneous shutdown gates' insertion based on simulated annealing (SA) and a force-directed TSV placer. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. We use shutdown gates to save clock trees' dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3DICs.
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